Backplane Simulation Part II

Faster PCB designs are by nature more sophisticated and delicate. At higher clock speeds, the PCB demands cleaner signal transmission without compromising the stability of the system. This is where Signal Integrity engineering comes into play. Simply put, signal integrity studies the design of high-speed circuits that can accommodate cleaner signals passing through them. Cleaner signals, in turn, enable engineers to identify and minimize sources of distortion in data transmission, which could otherwise disrupt timing of the digital logic. Signal integrity issues such as reflections, cross talk, frequency dependent transmission line loss and dispersion can significantly lead to poorer system performance propagating through the interconnect. These SI issues arise from via, power/ground coupling, RLC effects in signal lines, etc.

To ensure customers the optimum performance, backplane simulation/characterization studies can be performed. For characterization, two types of test can be performed: time-domain and frequency-domain tests. A typical set of time domain tests includes impedance, delay, skew, rise time degradation and time domain crosstalk. A typical tests set of frequency domain tests includes insertion loss (S21), return loss (S11) and frequency domain crosstalk.

Bustronic has just finished the 5-slot ATCA characterization by taking both time and frequency domain measurements. We were able to show that the 5-slot ATCA backplane performance was well within the specified requirements, even taking the worst-case scenarios. (-More-)