ANNOUNCING VXS PROCESSOR MESH ARCHITECTURE

First Implementation of 25 FPGAs Delivering 112.5 GB/s Throughput In a Single Chassis

Fremont CA - February 17, 2005 - Elma Bustronic of Fremont CA has announced a new VXS, VITA 41-based mesh architecture. The VXS Processor Mesh architecture will be proposed to VITA (VME International Trade Association) by the Companies as a new standard to define alternative backplane topologies for VXS. The VXS Processor Mesh is a powerful architecture with bandwidth that can deliver 112.5 GB/s of aggregate throughput within the processing mesh in a single chassis. This is a throughput improvement of 6x over currently available technology.

Elma Bustronic has also announced the industry’s first 12-slot backplane to implement the VXS Processor Mesh. Developed to enable a switch/processor mesh technology for applications which require multiple boards for application processing, this hybrid backplane implements two VME64x slots, three VME64x / VXS payload slots, and six VXS switch slots. Each switch slot implements twenty x 4 links for a total of 25 GB/s per switch slot. The system architecture supports up to 7.5 GB/s of throughput between the I/O front end and the processing mesh and a total of 112.5 GB/s of aggregate throughput within the processing mesh itself.

“The VXS switch / processor mesh architecture clearly demonstrates both the longevity and expandability of the VME platform for high performance embedded computing. In one system, a user could simultaneously use four stages of interconnect evolution: VME64, RACE++, VXS payload and VXS switch cards,” comments Andy Reddig, president and CTO of TEK Microsystems, Inc. “With such a wide range of performance, VXS offers the user a unique combination of leading edge performance without compromising existing hardware and software investments or the ability to deploy incremental upgrades.”

Michael Munroe a technical product specialist for Elma Bustronic Corp. comments, “We consider the VXS Processor Mesh an ‘instant architecture’ because it does not define any new backplane pin-assignments beyond those already defined within the VITA 41.0 base specification. But with bandwidth capabilities exceeding 112.5 GB/s of aggregate throughput within the processing mesh, we have the most robust offering for demanding signal processing applications available on the market today.”